mirror of
https://github.com/ps5-linux/ps5-linux-loader.git
synced 2026-05-09 00:24:16 +00:00
cleaning + notifications + autosleep
This commit is contained in:
@@ -117,8 +117,7 @@ static void patch_hv(void) {
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}
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// Install hv_shellcode 2
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uint64_t hv_shellcode = cave_hv;
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memcpy((void *)PHYS_TO_DMAP(hv_shellcode), shellcode_hypervisor,
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memcpy((void *)PHYS_TO_DMAP(cave_hv_code), shellcode_hypervisor,
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shellcode_hypervisor_len);
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// Jump to shellcode final identity mapping
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@@ -130,8 +129,8 @@ static void patch_hv(void) {
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// Update code cave in hv 1:1 region
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*(uint32_t *)(&shellcode_jmp[3]) = (uint32_t)args.hv_code_cave_pa;
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// Just patch the VMEXIT handler directly, avoiding all checks (0x6282b45d)
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memcpy(PHYS_TO_DMAP(args.hv_handle_vmexit_pa), shellcode_jmp,
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// Just patch the VMEXIT handler directly, avoiding all checks
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memcpy((void *)PHYS_TO_DMAP(args.hv_handle_vmexit_pa), shellcode_jmp,
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sizeof(shellcode_jmp));
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uint8_t shellcode_identity_and_jmp[] = {
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@@ -149,7 +148,7 @@ static void patch_hv(void) {
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*(uint64_t *)(&shellcode_identity_and_jmp[15]) = cave_hv_code;
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// Install shellcode 1 to update CR3 and jump to main HV shellcode
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memcpy(PHYS_TO_DMAP(args.hv_code_cave_pa), shellcode_identity_and_jmp,
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memcpy((void *)PHYS_TO_DMAP(args.hv_code_cave_pa), shellcode_identity_and_jmp,
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sizeof(shellcode_identity_and_jmp));
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}
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@@ -157,7 +156,7 @@ void boot_linux(void) {
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patch_hv();
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memcpy((void *)PHYS_TO_DMAP(0xC0000), g_vbios, 0x10000);
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memcpy((void *)PHYS_TO_DMAP(0xC0000), (void *)g_vbios, 0x10000);
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// Enable DP phys link.
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dp_enable_link_phy(4, 30);
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@@ -3,12 +3,6 @@
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#include <stdint.h>
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#define cave 0x100000000ULL
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#define cave_hv_paging cave
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#define cave_hv cave_hv_paging + 0x3000
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#define cave_linux cave_hv + 0x2000
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#define PAGE_SIZE 4096
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#define ALIGN_UP(size, align) (((size) + (align) - 1) & ~((align) - 1))
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static int dp_enable_link_phy(int lanenum, int linkrate);
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@@ -55,7 +55,7 @@ __attribute__((section(".entry_point"))) uint32_t main(uint64_t add1,
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// Reconfigure IOMMU calling the HV
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int ret = ((uint64_t(*)(uint64_t, uint64_t, uint64_t, uint64_t,
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int *))args_ptr->fun_hv_iommu_set_buffers)(
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iommu_cb2_pa, iommu_cb3_pa, iommu_eb_pa, &unk, &n_devices);
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iommu_cb2_pa, iommu_cb3_pa, iommu_eb_pa, (uint64_t) &unk, &n_devices);
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if (ret != 0) {
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putc_uart(args_ptr->dmap_base, 'I');
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@@ -126,7 +126,7 @@ __attribute__((section(".entry_point"))) uint32_t main(uint64_t add1,
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// Re-do this to force a VMEXIT without HV injecting faults
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((uint64_t(*)(uint64_t, uint64_t, uint64_t, uint64_t,
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int *))args_ptr->fun_hv_iommu_set_buffers)(
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iommu_cb2_pa, iommu_cb3_pa, iommu_eb_pa, &unk, &n_devices);
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iommu_cb2_pa, iommu_cb3_pa, iommu_eb_pa, (uint64_t) &unk, &n_devices);
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((uint64_t(*)(void))args_ptr->fun_hv_iommu_wait_completion)();
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putc_uart(args_ptr->dmap_base, 'B');
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@@ -195,7 +195,7 @@ void halt(void) { __asm__ __volatile__("hlt"); }
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// Submit a single 16-byte command and wait for completion
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__attribute__((noinline, optimize("O0"))) void
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iommu_submit_cmd(shellcode_kernel_args *args_ptr, uint64_t *cmd) {
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iommu_submit_cmd(volatile shellcode_kernel_args *args_ptr, uint64_t *cmd) {
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// Read the offset of current tail of command list
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uint64_t curr_tail = *(
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(uint64_t *)args_ptr->iommu_mmio_va +
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@@ -206,7 +206,7 @@ iommu_submit_cmd(shellcode_kernel_args *args_ptr, uint64_t *cmd) {
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// We write the command in the current empty entry
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uint64_t *cmd_buffer =
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args_ptr->iommu_cb2_va + curr_tail / 8; // Downscale the size of the ptr
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(uint64_t *)args_ptr->iommu_cb2_va + curr_tail / 8; // Downscale the size of the ptr
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// Copy 0x10 bytes (CMD Size)
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cmd_buffer[0] = cmd[0];
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cmd_buffer[1] = cmd[1];
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@@ -224,7 +224,7 @@ iommu_submit_cmd(shellcode_kernel_args *args_ptr, uint64_t *cmd) {
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// Write 8 bytes to a physical address using IOMMU completion wait store
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__attribute__((noinline, optimize("O0"))) void
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iommu_write8_pa(shellcode_kernel_args *args_ptr, uint64_t pa, uint64_t val) {
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iommu_write8_pa(volatile shellcode_kernel_args *args_ptr, uint64_t pa, uint64_t val) {
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uint32_t cmd[4] = {0};
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cmd[0] = (uint32_t)(pa & 0xFFFFFFF8) | 0x05;
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cmd[1] = ((uint32_t)(pa >> 32) & 0xFFFFF) | 0x10000000;
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@@ -234,7 +234,7 @@ iommu_write8_pa(shellcode_kernel_args *args_ptr, uint64_t pa, uint64_t val) {
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}
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__attribute__((noinline, optimize("O0"))) void
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patch_vmcb(shellcode_kernel_args *args_ptr) {
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patch_vmcb(volatile shellcode_kernel_args *args_ptr) {
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for (int i = 0; i < 16; i++) {
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uint64_t pa = args_ptr->vmcb[i];
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// args_ptr->fun_printf("Patching core: %02d VMCB_PA: 0x%016lx\n", i,
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@@ -281,16 +281,17 @@ __attribute__((noinline, optimize("O0"))) int tmr_disable(uint64_t dmap) {
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return 0;
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}
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void init_global_pointers(shellcode_kernel_args *args_ptr) {
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void init_global_pointers(volatile shellcode_kernel_args *args_ptr) {
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memcpy(&args, args_ptr, sizeof(args));
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memcpy(&args, (void *)args_ptr, sizeof(args));
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printf = args.fun_printf;
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smp_rendezvous = args.fun_smp_rendezvous;
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smp_no_rendevous_barrier = args.fun_smp_no_rendevous_barrier;
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printf = (void (*)(const char *, ...)) args.fun_printf;
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smp_rendezvous = (void (*)(void (*)(void), void (*)(void),
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void (*)(void), void *)) args.fun_smp_rendezvous;
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smp_no_rendevous_barrier = (void (*)(void)) args.fun_smp_no_rendevous_barrier;
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transmitter_control = args.fun_transmitter_control;
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mp3_initialize = args.fun_mp3_initialize;
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mp3_invoke = args.fun_mp3_invoke;
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transmitter_control = (int (*) (int, void*)) args.fun_transmitter_control;
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mp3_initialize = (int (*) (int)) args.fun_mp3_initialize;
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mp3_invoke = (int (*) (int, void*, void*)) args.fun_mp3_invoke;
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g_vbios = args.g_vbios;
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}
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@@ -13,11 +13,8 @@ uint64_t (*kernel_va_to_pa)(uint64_t va);
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uint32_t (*hv_iommu_set_buffers)(uint64_t cb2_pa, uint64_t cb3_pa,
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uint64_t eb_pa, uint64_t unk, int *n_devices);
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uint32_t (*hv_iommu_wait_completion)(void);
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void (*smp_rendezvous)(void (*setup_func)(void *), void (*action_func)(void *),
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void (*teardown_func)(void *), void *arg);
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void (*smp_rendezvous_cpus)(cpuset_t map, void (*setup_func)(void *),
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void (*action_func)(void *),
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void (*teardown_func)(void *), void *arg);
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void (*smp_rendezvous)(void (*setup_func)(void), void (*action_func)(void),
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void (*teardown_func)(void), void *arg);
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void (*smp_no_rendevous_barrier)(void);
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// We are being called instead of AcpiSetFirmwareWakingVector from
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@@ -44,8 +41,7 @@ uint64_t rdmsr(uint32_t msr);
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uint32_t tmr_read(uint64_t dmap, uint32_t addr);
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void tmr_write(uint64_t dmap, uint32_t addr, uint32_t val);
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int tmr_relax(void);
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int tmr_disable(uint64_t dmap);
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// Command buffer MMIO offsets
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#define IOMMU_MMIO_CB_HEAD 0xa000
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@@ -57,15 +53,16 @@ int tmr_relax(void);
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#define IOMMU_CMD_ENTRY_SIZE 0x10
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// Submit a single 16-byte command and wait for completion
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void iommu_submit_cmd(shellcode_kernel_args *args_ptr, uint64_t *cmd);
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void iommu_submit_cmd(volatile shellcode_kernel_args *args_ptr, uint64_t *cmd);
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// Write 8 bytes to a physical address using IOMMU completion wait store
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void iommu_write8_pa(shellcode_kernel_args *args_ptr, uint64_t pa,
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void iommu_write8_pa(volatile shellcode_kernel_args *args_ptr, uint64_t pa,
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uint64_t val);
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void patch_vmcb(shellcode_kernel_args *args_ptr);
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void patch_vmcb(volatile shellcode_kernel_args *args_ptr);
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#define NULL (void *)0
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void vmmcall_dummy(void);
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void halt(void);
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void init_global_pointers(volatile shellcode_kernel_args *args_ptr);
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#endif
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@@ -60,8 +60,8 @@ uint64_t va_to_pa_custom(uint64_t va, uint64_t cr3_custom) {
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__attribute__((noinline, optimize("O0"))) uint32_t putc_uart(uint64_t dmap,
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uint8_t tx_byte) {
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volatile uint32_t *uart_tx = dmap + 0xc1010104ULL;
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volatile uint32_t *uart_busy = dmap + 0xc101010cULL;
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volatile uint32_t *uart_tx = (uint32_t *) (dmap + 0xc1010104ULL);
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volatile uint32_t *uart_busy = (uint32_t *) (dmap + 0xc101010cULL);
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uint64_t timeout = 0xFFFFFFFF;
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do {
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timeout--;
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