Add RP1 grounds. Identify PCIe clock

CM5.kicad_sym

@@ -8380,7 +8380,7 @@
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@@ -8398,7 +8398,7 @@
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@@ -8416,7 +8416,7 @@
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@@ -8452,7 +8452,7 @@
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@@ -8470,7 +8470,7 @@
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@@ -8488,7 +8488,7 @@
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@@ -8506,7 +8506,7 @@
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@@ -8920,7 +8920,7 @@
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@@ -8938,7 +8938,7 @@
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@@ -12345,7 +12345,7 @@
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CM5RevEng.kicad_pcb

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 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "0863cd40-6d03-4438-9520-d6c4ca35bad5")
 		)
 		(pad "L6" smd circle
@@ -10383,6 +10422,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "e1d784ee-eab7-4d27-989e-75bb7ee6d72d")
 		)
 		(pad "L8" smd circle
@@ -10390,6 +10432,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "ecd8df0c-ba18-49a4-bb3e-918e12ab79ab")
 		)
 		(pad "L9" smd circle
@@ -10397,6 +10442,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "5c4d352a-e430-4ba8-a997-edf063da4df2")
 		)
 		(pad "L10" smd circle
@@ -10732,6 +10780,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "6a9fb976-2b70-4d9c-803e-7cafc0980979")
 		)
 		(pad "N16" smd circle
@@ -11274,6 +11325,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "cf0f5aaf-534c-49dc-ba0c-a19e2857d3dd")
 		)
 		(pad "V2" smd circle
@@ -11435,6 +11489,9 @@
 			(size 0.24 0.24)
 			(property pad_prop_bga)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 2 "GND")
+			(pinfunction "GND")
+			(pintype "power_in")
 			(uuid "427835e7-8af2-41d0-8cbf-2289ebf56bbc")
 		)
 		(embedded_fonts no)
@@ -101749,7 +101806,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Value" "??25MHz??"
+		(property "Value" "25MHz"
 			(at 0 -1.57 90)
 			(layer "B.Fab")
 			(uuid "ab24c2e5-e2e8-42b2-8d43-521e2a0fdbc0")

CM5RevEng.kicad_prl

@@ -26,7 +26,7 @@
       "otherItems": false,
       "pads": false,
       "text": false,
-      "tracks": false,
+      "tracks": true,
       "vias": false,
       "zones": false
     },
@@ -49,8 +49,8 @@
       "conflict_shadows",
       "shapes"
     ],
-    "visible_layers": "ffffffff_ffffffff_fffffff5_575555f5",
+    "visible_layers": "ffffffff_ffffffff_fffffff5_57555555",
-    "zone_display_mode": 1
+    "zone_display_mode": 0
   },
   "git": {
     "repo_type": "",

README.md

@@ -66,6 +66,11 @@ The original board has no designators, so the ones in this design are
 made up, with the exception of the test points, which are documented
 in the official RPi datasheet.
 
+The 5V input goes through a hot-swap circuit with a series pass MOSFET. Since
+there is a test point on either side of the MOSFET and the part number is
+known (DMG7430LFG), you could monitor the voltage across and compute the
+supply current based on the MOSFET RDSON.
+
 ## Board Stackup
 
 By very carefully sanding through the board one layer at a time, I figured
@@ -167,6 +172,47 @@ coordinate, and subtract the Y coordinate from 100.
 | TP76      | 42.9  | 36.1  | ETH3\_N |
 | TP77      | 14.37 | 19.52 | +5V     | Raw 5V power to board. |
 
+## RP1 Pinout Mysteries
+
+There are some pins that have not been identified because they're not connected
+on the CM5:
+
+| Pin | Guess |
+|-----|-------|
+| A2  | |
+| B3  | |
+| C2  | |
+| C3  | |
+| C4  | |
+| D1  | |
+| E3  | |
+| E10  | |
+| E15  | |
+| F1  | |
+| F2  | |
+| F3  | |
+| F7  | |
+| G1  | |
+| G2  | |
+| H1  | |
+| H3  | |
+| H7  | |
+| H17 | USB 2.0? |
+| H18 | USB 2.0? |
+| J15  | |
+| J17  | |
+| L13  | |
+| L15  | |
+| M17  |USB 2.0? |
+| M18  |USB 2.0? |
+| R4  | |
+| T3  | |
+| T4  | |
+| T13  | |
+| T14  | |
+| V2  | |
+| V3  | |
+
 ## Future Work
 
 * PCIe (BCM2712 to RP1) net identification